Storage devices, such as flip-flops and registers, introduce gate delays between the time data is known and the time that the data is latched and then propagated to the output driver. Look-ahead circuits are often employed to reduce this propagation delay, thereby enhancing the speed of the data output operation.
The specific problem to which the invention is applicable is an improved look-ahead technique for reducing the delays associated with storage devices, while still guaranteeing the required synchronism with the controlling clock pulses. Ideally, such an improved look-ahead technique could be used in both the HI and LO phases of the storage operation.
The look-ahead concept is generally applicable to synchronized devices where a result or output is known prior to the associated control or clocking event that synchronizes the device. For flip-flops, the typical approach takes advantage of their two stage, master/slave configuration in which data is first latched into a master section, and then propagated to the slave section and thence to an output driver for the DATA line. This storage operation involves three gate delays--the internal clock, the master section and the slave section--which in current technology translates typically into about 6 ns (nanoseconds), although 4 ns devices are available.
Look-ahead operations are performed by using the logic levels of the master section to generate an output value, thereby bypassing the slave section and the associated propagation delay. By using the device itself for look-ahead operations, synchronism is maintained with the controlling clock.
However, this look-ahead technique can only be used for the one phase of the storage operation. Specifically, when the associated output transistor is on, the low-going edge that latches the master can also be used to switch the output transistor off--this is a LO phase look-ahead technique that cannot be used when the output transistor is off because adding an inverter to use the low-going edge in the master to switch the output transistor on (HI phase) would introduce a gate delay that would cancel the time saved by looking ahead of the slave section.
Moreover, even for LO phase look-ahead, the flip-flop is not completely bypassed, but rather, only the gate delay associated with the slave section is avoided. The gate delays associated with the internal clock and the master section are still present.
Thus, using current look-ahead techniques, 6 ns devices can operate in the range of 4 or 5 ns for the LO phase.
Accordingly, a need exists for an improved look-ahead technique for synchronized devices, such as storage devices, that bypasses the device while maintaining synchronism with the control/clock.